In various fields of application, delay locked loops (also called DLLs) are used. The delay of an input clock signal is typically locked in the delay locked loop such that the delayed input clock signal is delayed by precisely one clock cycle relative to the input clock signal. This is typically done by comparing the signal edges of the input clock signal and of the delayed input clock signal using a phase frequency detector. If the adjusted delay of the delay locked loop is too great, however, it may arise that the delay locked loop is locked for a delay of two or more clock cycles. An incorrect lock state of this kind in the delay locked loop is also called a false lock state.
There is therefore a need for efficient techniques for sensing a false lock state in a delay locked loop.